<'
unit switch_driver {
   inst_no : uint;
   event clk is rise('clk')@sim; 
   // This is real dump driver!!!
   drive_data(data : byte)@clk is {
     wait cycle;
      outf ("Driving port : %d\n",inst_no);
      outf ("    in  data : %d\n",data);
     'data_in(inst_no)'       = data;
     'data_in_valid(inst_no)' = 1;
     wait cycle;
     'data_in(inst_no)'       = 0;
     'data_in_valid(inst_no)' = 0;
     wait cycle;
      outf ("    out data : %d\n",data);
     // Check if the data is coming out
     if ('data_out_ack(inst_no)' == 1) {
       check that data == 'data_out(inst_no)';
     } else {
       out ("There seems to be a error in DUT");
     };
   };
};

unit switch_fabric {
  ports: list of switch_driver is instance; 
  keep ports.size() == 6; 
  // Assign path and unique number to each drive instance 
  keep for each in ports {  
    .hdl_path() == ""; 
    .inst_no    == index;
  }; 
  // Have clock reference
  event clk is rise('clk')@sim; 
  // Drive traffic into switch
  txgen()@clk is {
    wait [10]*cycle;
    ports[0].drive_data(10);
    ports[1].drive_data(11);
    ports[2].drive_data(12);
    ports[3].drive_data(13);
    ports[4].drive_data(14);
    ports[5].drive_data(15);
    wait [10]*cycle;
    stop_run();
  };
};

extend sys {
  switch_fabric :  switch_fabric is instance;
  keep switch_fabric.hdl_path() == "unit_example";
  run() is also {
    start switch_fabric.txgen();
  };
};
'>